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The KSZMNX offers the industry-standard GMII/MII Media Independent Interface (GMII) is compliant to the IEEE Specification. Dave Fifield [email protected] GMII Electrical Specification IEEE Interim Meeting, San Diego, January N. Interface) for connection to GMII/MII MACs in Gigabit . Clarified power cycling specification to have all supply voltages to the KSZMNX.

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At power up, specifiation autonegotiationthe PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface. It contains a bitmask with the following meaning: The standard MII features a small set of registers: Source-synchronous clocking is used: Archived from the original on Current revisions of IEEE This may be used to abort a frame when some problem is detected after transmission has already started.

Ethernet Computer buses Serial buses. These registers can be used to configure the device say “only gigabit, full duplex”, slecification “only full duplex” or can be used to determine the current operating mode.

At least the standard says the signals need not be treated as transmission lines. Typically used for on-chip connections; in chip-to-chip usage mostly replaced by XAUI.

The RMII signals are treated as lumped signals rather than transmission lines; no termination or controlled impedance is necessary; output drive and thus slew rates need to be as slow as possible rise times from 1—5 ns to permit this.

Some of the preamble nibbles may be lost. Retrieved from ” https: This arrangement allows the MAC to operate without having to be aware of the link speed.

Drivers should be able to drive 25 pF of capacitance which allows for PCB traces up to 0.


Media-independent interface – Wikipedia

The transmit enable signal is specificatuon high during frame transmission and low when the transmitter is idle. From Wikipedia, the free encyclopedia. Input high threshold is 2. Being media independent means that different types of PHY devices for connecting to different media i. By using this site, you agree to the Terms of Use and Privacy Policy.

However, at 1 ns edge rates a trace longer than about 2. Given trends in the semiconductor industry and the fact that both ICs are usually on the same board, lack of 5 V tolerance is probably very common, and chips that actually drive 5 V are probably even rarer.

Transmit and receive path each use one differential pair for data and another differential pair for clock.

On the other hand, newer devices may support 2. There are 32 addresses, each containing 16 bits. For this reason, the reduced media independent interface was developed. The media-independent interface MII was originally defined as a standard interface to connect a Fast Ethernet i. The original MII transfers network data using 4-bit nibbles in each direction 4 transmit data bits, 4 receive data bits.

Transmit error may be sspecification for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid.

This page was last edited on 19 Novemberat Four things were changed compared to the Specifiaction standard to achieve this:.

Media-independent interface

Data is sampled on the rising edge only i. This requires the PCB to be designed to add a 1.

The management interface controls the behavior of the PHY. If a collision is detected, COL also goes high while the collision persists. The MAC may omit the signal if specificstion has no use for this functionality, in which case the signal should be tied low for the PHY. When no clock can be gkii i. The specification states that inputs should be 5 V tolerant, however, some popular chips with RMII interfaces are not 5 V tolerant. Retrieved 20 April This interface requires 9 signals, specificafion MII’s Ethernet family of local area network technologies.


There is no signal which defines whether the interface is in full or half duplex gmii, but both the MAC and the PHY need to agree. Specificatuon original MII design has been extended to support reduced signals and increased speeds. For receive, two data values are defined: As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy check CRC.

The receiver clock is much simpler, with only one clock, which is recovered from the incoming data. More recently, raising transmit error outside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling.

The receive clock is recovered from the incoming signal during frame reception. The first 16 addresses have a defined specififation, [7] while the others are device specific. Received clock signal recovered from incoming received data. Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY.

TTL signal levels are used for 5 V or 3. It is not to be confused with RM2.

This means a slight modification of the definition of CRS: